Course Details - Vedanta Circuits

Course Overview

Complete functional verification flow covering RTL design, logic synthesis, and advanced verification methodology using SystemVerilog and UVM.

This program is designed to bridge the gap between academic education and industry requirements. The curriculum starts from basics and scales up to industry grade designs.

Learning Outcomes

Write efficient, synthesizable RTL and functional code.

Build robust verification environments from scratch.

Perform detailed functional and code coverage analysis.

Master the Linux environment and advanced scripting.

Course Curriculum

Structured modules with hands-on projects. Download the PDF brochure for the full syllabus.

1. Module 1: Digital Electronics & RTL Design (Verilog)

2. Module 2: Advanced Verification using SystemVerilog

3. Module 3: Verification Methodology using UVM

4. Module 4: Industry Grade Projects & Protocols (AXI, AHB)

Module 1

4-bit ALU Design

Design and verify a Arithmetic Logic Unit using RTL.

Module 2

FIFO Controller Verification

Build a testbench for a parameterized FIFO memory.

Module 3

UART Protocol Design

RTL implementation and verification of UART logic.

Module 4

Bus Verification

Advanced interface verification protocols.

Major Project

SoC Verification

End-to-end multi-protocol SoC verification.

Capstone

Chip Tape-out

RTL to gate-level netlist sign-off.

Full Module Breakdown

Module 1 - Digital Electronics & Fundamentals

Number systems and Boolean Algebra
Combinational Logic Design
Sequential Logic Design

Module 2 - Verilog HDL & RTL Design

Introduction to Verilog HDL
Writing synthesizable RTL code

Module 5 - Interview Preparation

Aptitude and Technical written tests
1-on-1 mock interviews

VLSI Design & Verification