Course Details - Vedanta Circuits

Course Overview

Deep dive into Floorplanning, Placement, CTS, Routing, Power Grid Design, and Static Timing Analysis (STA) signoff using industry-standard EDA tools like Cadence Innovus.

This program is designed to bridge the gap between academic education and industry requirements. The curriculum starts from basics and scales up to industry grade designs.

Learning Outcomes

Understand structural gate-level layout and physical properties.

Master Cadence Innovus for PnR flows and floorplanning.

Resolve routing congestion, setup, and hold timing violations.

Run DRC/LVS physical verification and static timing analysis.

Course Curriculum

Structured modules with hands-on projects. Download the PDF brochure for the full syllabus.

1. Module 1: Physical Design Flow & Inputs

2. Module 2: Floorplanning & Power Planning

3. Module 3: Placement, CTS, and Routing

4. Module 4: STA Signoff & Physical Verification (DRC/LVS)

Module 1

Floorplanning & Power Grid

Generate robust IR drop optimal power grid network.

Module 2

Placement & Optimization

Optimize logic gate distribution for timing and area.

Module 3

Clock Tree Synthesis

Build low skew symmetric clock distributions.

Module 4

Routing & Signoff

Route interconnections and solve DRC violations.

Major Project

Block Level PnR

Full block level floorplan to GDSII layout flow.

Capstone

Multi-Corner STA

Signoff analysis under multiple operating conditions.

Full Module Breakdown

Module 1 - Physical Design Flow & Inputs

Synthesis to Netlist mapping
Technology libraries (.lib, LEF)
Design constraints (SDC)

Module 2 - Floorplanning & PnR

Block sizing and aspect ratios
Pin placement and blockages
Power planning & IR drop analysis

Module 3 - Timing Closure & Verification

Static Timing Analysis (STA) setup & hold
Physical verification DRC/LVS on Calibre
Parasitic extraction (RCX)

Physical Design