Course Details - Vedanta Circuits

Course Overview

Specialized module focusing entirely on advanced functional verification architectures, assertions, coverage-driven verification, and protocol-specific verification IPs.

This program is designed to bridge the gap between academic education and industry requirements. The curriculum starts from basics and scales up to industry grade designs.

Learning Outcomes

Construct object-oriented verification testbenches in SystemVerilog.

Write functional coverage groups and assertions for protocol validation.

Architect modular, reusable UVM environments with agents and drivers.

Verify complex interfaces like PCIe, AXI, and APB protocols.

Course Curriculum

Structured modules with hands-on projects. Download the PDF brochure for the full syllabus.

1. Module 1: Advanced OOP & SystemVerilog Assertions (SVA)

2. Module 2: Functional Coverage & Constraint Randomization

3. Module 3: Custom UVM Verification Environments

4. Module 4: Case Study on Multi-Core SOC Verification

Module 1

OOP Testbench

Build a class-based SystemVerilog testbench layout.

Module 2

SVA Assertions

Write interface assertions for protocol compliance.

Module 3

UVM Agent Design

Develop a reusable UVM sequencer, driver, and monitor.

Module 4

AXI Protocol verification

Construct test scenario suites for AXI4 interconnects.

Major Project

Multicore SoC Verification

Integrate multiple verification components on an SoC environment.

Capstone

Coverage Closure

Attain 100% functional and code coverage metrics.

Full Module Breakdown

Module 1 - Advanced OOP & Assertions

Classes, inheritance, polymorphism
SystemVerilog Assertions (SVA) writing
Virtual interfaces and testbench linking

Module 2 - UVM Core Framework

UVM phases and reporting mechanism
Configuration database (config_db)
Transaction-level modeling (TLM) ports

Module 3 - Coverage & Protocol verification

Functional coverage and cross coverage
Verification IP (VIP) usage
Simulation debug techniques using Verdi

ASIC Verification