Course Overview
Learn to map and partition complex designs onto modern Xilinx Vivado and Intel Quartus FPGA boards. Focus on timing closure and hardware-software co-design.
This program is designed to bridge the gap between academic education and industry requirements. The curriculum starts from basics and scales up to industry grade designs.
Learning Outcomes
Synthesize and map RTL designs to FPGA logic blocks (LUTs, flip-flops).
Manage clock domain crossings and define timing constraints (SDC/XDC).
Integrate soft-core processors and interface peripherals over AXI buses.
Implement hardware-in-the-loop debugging with integrated logic analyzers.
Course Curriculum
Structured modules with hands-on projects. Download the PDF brochure for the full syllabus.
1.
Module 1: FPGA Architecture & Vivado Flows
2.
Module 2: Constraints & Clock Domain Crossing
3.
Module 3: Timing Closure & IP Integrations
4.
Module 4: Embedded Soft Cores (MicroBlaze/Nios)
Module 1
LED Controller on Board
Synthesize and implement clock dividers on physical FPGA.
Module 2
ILA Logic Analyzer
Integrate Xilinx ILA core to debug active hardware.
Module 3
CDC Synchronizer
Design clock domain crossing circuits with low latency.
Module 4
Soft-Core MicroBlaze
Instantiate MicroBlaze and load C code on processor.
Major Project
Video Processing Pipeline
Develop custom frame buffers and interface HDMI on FPGA.
Capstone
Timing Closure
Resolve negative slack and clean CDC warnings on Vivado.
Full Module Breakdown
- Logic Elements (LE), DSP slices, block RAMs
- Synthesis, Placement, and Routing on Vivado
- Bitstream generation and hardware programming
- Setup and hold constraints on FPGA
- False paths, multicycle paths, clock relationships
- CDC synchronizers and FIFO buffers
- Soft-core processors (MicroBlaze)
- AXI-Lite and AXI-Stream peripherals
- Embedded C programming on hardware