Course Overview
Master transistor-level custom layout techniques, matching methods, ESD protection structures, and post-layout parasitics extraction using Cadence Virtuoso.
This program is designed to bridge the gap between academic education and industry requirements. The curriculum starts from basics and scales up to industry grade designs.
Learning Outcomes
Understand custom layout grids and transistor spacing constraints.
Implement layout matching techniques (Common Centroid, Interdigitation).
Prevent latch-up and design robust ESD protection structures.
Extract post-layout parasitics (RC) and perform back-annotation simulations.
Course Curriculum
Structured modules with hands-on projects. Download the PDF brochure for the full syllabus.
1.
Module 1: CMOS Physics & Device Characteristics
2.
Module 2: Layout Matching Techniques (Common Centroid)
3.
Module 3: DRC/LVS/RCX Verification Flow
4.
Module 4: High-Performance Amplifier & Bandgap Layouts
Module 1
Inverter layout
Custom physical layout of CMOS inverter in Virtuoso.
Module 2
Matched Differential Pair
Design symmetric layout for low mismatch amplifiers.
Module 3
Current Mirror Layout
Create matched current mirror array layouts.
Module 4
Guard Rings & Latch-up prevention
Implement guard rings for noise isolation.
Major Project
Operational Amplifier Layout
Complete layout of a two-stage Op-Amp with RC extraction.
Capstone
Bandgap Reference Layout
Layout of temperature stable bandgap reference blocks.
Full Module Breakdown
- Design rules, spacing, enclosure constraints
- MOS transistor geometries and routing metals
- Contact and via density requirements
- Common Centroid, Interdigitation, Dummy cells
- Guard rings, deep N-well isolation
- Latch-up prevention guidelines
- DRC/LVS verification on Calibre
- Post layout parasitic RC extraction (PEX)
- Post layout simulation comparison